1. Field of the Invention
The present invention relates to failure detection, and specifically to a method and apparatus for failure detection of logic nodes within an integrated device utilizing functional test vectors and scan mode.
2. Description of the Related Art
As the technology for manufacturing integrated circuits advances, more logic functions are included in a single integrated circuit device. Modem integrated circuit (IC) devices include large numbers of gates on a single semiconductor chip, with these gates interconnected so as to perform multiple and complex functions. The manufacture of such circuits incorporating such Very Large Scale Integration (VLSI) requires that the fabrication of the circuit be error free, as some manufacturing defects may prevent it from performing all of the functions that it is designed to perform. This requires verification of the design of the circuit and also various types of electrical testing after the IC is manufactured.
However, as the complexity of the circuit increases, so does the cost and difficulty of verifying and electrically testing each of the devices in the circuit. Electrical testing requires that each gate in a VLSI circuit functions properly. Therefore, each gate needs to individually and in conjunction with the other gates in the circuit function properly in all possible combinations of operations. Typically, electrical testing is performed by automated testing equipment (ATE) that employs test vectors to perform the desired tests. A test vector describes the desired test input (or signals), associated clock pulse (or pulses), and expected test output (or signals) for every package pin during a period of time, often in an attempt to xe2x80x9ctestxe2x80x9d every node of each gate. For complex circuitry, this may involve a large number of test vectors and accordingly a long test time.
One way to address this problem is through design for test (DFT). The key concepts in DFT are controllability and observability. Controllability is the ability to set and reset the state of every node in the circuit. Observability is the ability to observe either directly or indirectly the state of any node in the circuit. The purpose of DFT is to increase the ability to control and observe internal and external nodes from external inputs/outputs.
DFT methods utilize various test circuits. One type of test circuit is a scan path or a scan loop in the logic circuit. A scan path or scan loop consists of a chain of synchronously clocked master/slave latches (or registers), each of which is connected to a particular node in the logic circuit. The scan latches can be loaded with a serial data stream, scan vectors, presetting the logic circuit nodes to a predetermined state. The logic circuit then can be exercised in normal fashion, with the result of the operation stored in its respective latch. A scan out operation serially unloads the contents of the latches and the result of the test operation at the associated nodes is analyzed for improper node operation.
Various automatic test pattern generation (ATPG) software allows for the creation of scan vectors. Scan vectors are efficient in detecting stuck at faults. A stuck at fault is if a particular node is xe2x80x9cstuckxe2x80x9d at a logic 0 or a logic 1 due to a manufacturing defect. For example, a node could be a stuck at one because the manufacturing defect caused the node to be shorted to a Vcc line.
However, scan vectors are not efficient in detecting speed-related defects because of the difficulty of observing every possible node in the IC design. Observability of every node in the IC design requires an unrealistic amount of silicon area, increased power consumption, and increased manufacturing costs.
Functional test vectors allow for increased coverage because of the ability to detect speed related defects because the IC is tested at functional speed. The difficulty in manually probing and detecting the failures for speed related defect increases as the IC industry continues to reduce the size of integrated chips and utilizes flip chip package technology. Flip chip package technology prevents access to the IC from the topside of the package. The only access to the IC in a flip chip package is from the backside (or underneath) the package. Thus, manual probing of the IC is difficult and time consuming.